您确定要运行模拟吗？
您的TB代码：
module RAM_IN (pix_val, indx);
input [0:5] indx;
output [31:0] pix_val;
reg [31:0] pix_val;
reg [31:0] in_ram [0:4];
always @ (indx)
pix_val = in_ram [indx];
initial
begin
$readmemb("in_ram.txt", in_ram);
end
endmodule
module tb;
reg [0:5] indx;
wire [31:0] pix_val;
RAM_IN ram_in(pix_val, indx);
initial
begin
indx = 'b0;
$monitor ($realtime, " Read Data = %0b" ,pix_val);
repeat(4)
begin
#10;
indx = indx + 1'd1;
end
$finish;
end
endmodule
使用相同的in_ram.txt。
Questasim：
QuestaSim-64 qverilog 10.4 Compiler .12 Dec 2
Start time: 18:27:01 on May 10,
qverilog me.v
-- Compiling module RAM_IN
-- Compiling module tb
Top level modules:
tb
Reading pref.tcl
# 10.4
# vsim -lib work tb -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt
# ** Note: (vsim-3812) Design is being optimized...
# // Questa Sim-64
# // Version 10.4 linux_x86_64 Dec 2
# //
# // Copyright 1991- Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.tb(fast)
# run -all
# 0 Read Data = 11111111000000000000000000000000
# 10 Read Data = 10010111000000000000000000000000
# 20 Read Data = 110110000000000000000000000000
# 30 Read Data = 111110000000000000000000000000
# ** Note: $finish : me.v(34)
# Time: 40 ns Iteration: 0 Instance: /tb
# End time: 18:27:02 on May 10,, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
和仿真：
readmemh函数引用的txt格式_memory - 在Verilog中 我尝试使用$ readmemb来读取.txt文件 但它仅在内存中加载xxxxx（不必担心） - 堆栈内存溢出...
